The present invention relates to a semiconductor integrated circuit, and, more particularly, a semiconductor integrated circuit device suitable for high-speed operation.
In an integrated circuit using CMOS transistors, characteristics fluctuation exists due to variations in transistor dimension caused by a fabrication process and a change in the environment, such as temperature or supply voltage, during operation.
As described in xe2x80x9c1994 symposium on VLSI technology digest of technical papersxe2x80x9d (June, 1994), pp. 13 to 14, as an MOS transistor becomes finer, fluctuation in basic parameters, such as a threshold value due to the characteristics fluctuation caused by a fabrication process, becomes larger.
FIG. 12 schematically shows delay of a CMOS circuit with respect to the device feature size of a MOS transistor and the range of variation. In designing a CMOS integrated circuit, the worst delay in FIG. 12 has to be considered. By an increase in the range of variation, even if the device becomes finer, high-speed operation is limited by the worst delay. If the delay of the CMOS circuit can be made xe2x80x9ctypicalxe2x80x9d or xe2x80x9cbestxe2x80x9d by suppressing the characteristics fluctuation, the high processing speed of the circuit can be promoted.
As a method of suppressing the characteristics fluctuation by improving the circuit, in Nikkei Electronics 7-28 (1997), pp. 113 to 126, a technique is described as follows: A leakage current of a monitor is measured and a substrate bias is changed so that the current becomes a constant value. Delay of a replica is also measured. A change in delay is detected, and the supply voltage is changed, thereby suppressing the characteristics fluctuation.
According to the technique described in Nikkei Electronics 7-28 (1997), pp. 113 to 126, the substrate bias is controlled so that the leakage current of the MOS transistor when the gate voltage is 0V becomes a constant value. Since the leakage current of the MOS transistor increases as the temperature rises, the threshold has to be increased by applying the substrate bias. In this case, there is a drawback such that the ON current of the MOS transistor conspicuously decreases by deterioration in mobility and increase in the threshold due to the temperature rise, and as a result, the processing speed of the circuit decreases. A filter having an inductance and a capacitance is formed outside of the chip and used to generate a supply voltage for delay control. Since it takes a few xcexc seconds until an output voltage of the filter is stabilized, stabilization time of a control signal is long, and the signal tends to be unstable. Consequently, control accuracy cannot be raised. When the capacitance and the inductance used for the filter are formed on the same chip on which a circuit to be controlled is also mounted, the fact that they occupy a large area becomes a problem.
Japanese Unexamined Patent Application No. 4-247653 discloses a concept such that a delay detector is provided to suppress delay variations of a gate circuit and the substrate bias of the gate circuit is controlled on the basis of the detection result.
Japanese Unexamined Patent Application No. 5-152935 also discloses a concept such that the substrate bias is controlled by using a capacitive filter and a charge pump to suppress device variations, thereby improving the yield.
Further, Japanese Unexamined Patent Application No. 8-274620 discloses a concept such that the delay amount of a circuit is detected by using a reference clock signal and the substrate bias of the circuit is controlled on the basis of the detection result.
It is an object of the invention to solve the problems of the conventional techniques.
More specifically, the inventors of the present invention have examined the problems in detail, which may occur when the conventional techniques are applied to a real semiconductor integrated circuit device, and propose the present invention. The present invention is to provide a semiconductor integrated circuit constructed by an MOS (MIS) transistor, in which characteristics fluctuation of a CMOS circuit is suppressed in short stabilization time and in a small area to thereby raise the control accuracy and improve the operating speed of the main circuit.
In order to achieve the subject, a semiconductor integrated circuit device as a representative embodiment of the invention includes a logic circuit for performing a predetermined process and a substrate-bias controller for supplying a substrate bias to an MIS transistor constructing the logic circuit. The logic circuit takes the form of an MIS transistor, and the substrate-bias controller supplies a suitable substrate bias to the MIS transistor in accordance with the characteristics fluctuation of the logic circuit. The threshold of the MIS transistor is changed by changing the substrate bias and the characteristics fluctuation of the logic circuit is suppressed. The characteristic of the logic circuit is detected as a delay, and the amount of change of the delay is converted into a digital amount. As a result, the substrate-bias controller can be constructed by a digital circuit, so that the stabilization time of the control voltage is shortened and the circuit scale is reduced.
A typical construction example of the invention is a semiconductor integrated circuit device including: a logic circuit for performing a predetermined process; a digital-to-analog converter for generating a substrate bias for controlling a threshold of an MIS transistor constructing the logic circuit; a voltage-controlled circuit for outputting a control signal in accordance with a delay signal; and a delay detector which can vary operating speed, characterized in that the delay detector receives a clock signal supplied from the outside and outputs a delay signal. The voltage-controlled circuit receives the delay signal of the delay detector and outputs a control signal according to delay time. The digital-to-analog converter receives the control signal supplied from the voltage-controlled circuit and generates a voltage according to the control signal, and the operating speed of the logic circuit and the delay detector is controlled by voltage supplied from the digital-to-analog converter.
In the example, since the main part of the controller deals with a digital signal, the circuit configuration is simple. The controller part and the circuit to be controlled can also be formed on different chips.
As a typical example of the circuits, the delay detector is comprised of a clock-duty modulator and a delay monitoring circuit. The voltage-controlled circuit is constructed by a delay comparator, the digital-to-analog converter is constructed by a substrate-bias generator, and the clock-duty modulator receives the clock signal from the outside and outputs a clock signal of an arbitrary clock duty ratio.
As another example, the delay monitoring circuit outputs an output signal of the clock-duty modulator with a predetermined delay. The delay comparator obtains a delay difference between the output signal of the clock-duty modulator and the output signal of the delay monitoring circuit by comparison, and outputs a signal according to the difference. The substrate-bias generator generates a substrate bias according to the output signal of the delay comparator, and the delay in both the logic circuit and the delay monitoring circuit is controlled by the substrate bias generated by the substrate-bias generator.
As another typical example, the delay detector is comprised of a divider and an oscillator, the voltage-controlled circuit is comprised of a phase-frequency detector and a phase-frequency controller, and the digital-to-analog converter is constructed by a voltage generator. The clock signal from the outside is supplied to the divider by which the frequency of the clock signal is optionally divided, the phase-frequency detector compares a phase and a frequency of a frequency-division signal of the divider with those of an output signal of the oscillator and produces an output signal according to the difference. The phase-frequency controller outputs a control signal in accordance with an output signal of the phase-frequency detector, the voltage generator generates a substrate bias in accordance with the control signal of the phase-frequency controller, and the operating speed of both the logic circuit and the oscillator is controlled by the substrate bias generated by the voltage generator.
Further, as a preferable example, a pMOS circuit and an nMOS circuit are separately controlled.
More specifically, the delay detector is comprised of a pMOS delay detector for detecting a change in the threshold of a pMOS transistor and an nMOS delay detector for detecting a change in the threshold of an nMOS transistor. Two voltage-controlled circuits and two digital-to-analog converters are prepared for the pMOS transistor and the nMOS transistor. The operating speed of the pMOS delay detector is controlled by a substrate bias for the pMOS transistor generated by the digital-to-analog converter for the pMOS transistor, and the operating speed of the nMOS delay circuit is controlled by the substrate bias for the nMOS transistor generated by the digital-to-analog converter for the nMOS transistor.
In the invention, by controlling the substrate bias of the transistor constructing the circuit, the threshold of the transistor is controlled, thereby controlling the operating speed of the circuit. In this case, when the threshold of the transistor decreases, what is called a subthreshold leakage current (leakage current between the gate and the source) increases. When the leakage current increases, the temperature of the circuit rises and the delay of the circuit increases.
In the case of decreasing the threshold of the transistor constructing the circuit to reduce the delay when the delay of the circuit is detected and increased, if no limiter is provided, the substrate bias is continuously applied in the direction of decreasing the threshold, so that there is a danger that an operating error in high temperature occurs.
According to the invention, there is consequently proposed a semiconductor integrated circuit device comprising a circuit to be controlled including at least one transistor, and a controller for controlling a substrate bias of the transistor in the circuit to be controlled, for changing the threshold of the transistor, wherein the controller has a limiter for controlling the substrate bias within a predetermined range.
As an example, the limiter has a leakage current detector for detecting leakage current of the transistor. When the leakage current increases to a predetermined value or larger, the substrate bias control of the controller is stopped.
In the case where the digital-to-analog converter for generating the substrate bias to control the threshold of the MIS transistor constructing the logic circuit is used, when the leakage current is increased to a predetermined value or larger, an output voltage of the digital-to-analog converter is fixed, thereby enabling the increase in the leakage current to be limited.
Further, in the invention, a detailed sequence to control the substrate bias is provided.
Specifically, in the invention, there is proposed a circuit device including a circuit to be controlled including a transistor and a controller for dynamically controlling a substrate bias of the transistor, characterized in that the circuit device performs operations in the following order:
(1) setting of the substrate bias of the transistor to a predetermined value,
(2) application of a supply voltage to the transistor, and
(3) dynamic control of the substrate bias of the transistor.
In this case, the controller can comprise a monitoring circuit for monitoring delay in the controlled circuit and a substrate-bias generator for controlling the substrate bias of the transistor on the basis of a signal from the monitoring circuit.
More specifically, there is provided a semiconductor integrated circuit device comprising a logic circuit for performing a predetermined process, two voltage stabilizers, a control voltage stable-state detector, a reset cancellation circuit, and an operation/non-operation switching circuit, characterized in that the substrate bias is supplied after the device is started. The first voltage stabilizer supplies a supply voltage after the substrate bias becomes stable, the second voltage stabilizer supplies a control signal to the semiconductor integrated circuit after the supply voltage becomes stable, and the control voltage stable-state detector detects the stable state of an output voltage for control of the semiconductor integrated circuit. The reset cancellation circuit sends a reset cancellation signal to the logic circuit when the control voltage stable-state detector detects the stable state to thereby cancel the reset state of the logic circuit and to allow the operation to start, and the operation/non-operation switching circuit switches validity/invalidity of the control of the semiconductor integrated circuit in accordance with the operation/non-operation switching signal, thereby preventing an erroneous operation of the logic circuit at the time of start-up or during operation.
In association with the increase in the functions of the integrated circuit device, there is a case such that it is effective to divide the circuit into a plurality of blocks and change the operating speed and the operating voltage block by block.
According to another mode of the invention, there is provided a semiconductor integrated circuit device comprising a logic circuit having at least first and second blocks, first and second speed controllers, and a clock generator, characterized in that different supply voltages are supplied to the first and second blocks, and the first and second speed controllers control the operating speeds of the logic circuit in the blocks in accordance with the supply voltages applied to the respective blocks.
As another mode of the invention with emphasis on reducing the power consumption of the circuit, there is provided a semiconductor integrated circuit device comprising a first circuit block to be controlled and a second circuit block to be controlled, characterized in that each of the circuits to be controlled is provided with a switch, and the supply of power to a transistor included in each of the circuits to be controlled is controlled by the switch. Each of the circuits to be controlled is provided with a controller, and the substrate bias of the transistor included in each of the circuits to be controlled is controlled by the controller.
The switch is controlled by, for example, a mode switching signal. By turning off the switch when the circuit is not operating, the leakage current of the FET in the circuit can be reduced. When the circuit is operating, the threshold of the FET is controlled by a dynamic control of the substrate bias of the transistor as described above, and the operating speed and the power consumption of the circuit can be set to proper values. For example, the controller detects the delay of the circuit to be controlled and controls the substrate bias of the transistor on the basis of the detection result.
It is also possible to apply different supply voltages to the circuits to be controlled.
As a layout of the circuit, the speed controller is comprised of the delay detector and the controller. When the delay detector is disposed in the block to be controlled, particularly, in the center of the block, the operating speed can be accurately detected.
As another mode of the invention, there is provided a semiconductor integrated circuit device comprising a logic circuit for performing a predetermined process, an input/output circuit for transmitting a signal to the logic circuit, and a speed controller for controlling the operating speed of the circuit, characterized in that the signal transmitting speed of the input/output circuit is controlled by the speed controller. Specifically, the speed controller controls the substrate bias of the transistor constructing the input/output circuit to change the threshold, thereby controlling the operating speed.
As another example, there is provided a semiconductor integrated circuit device comprising a logic circuit for performing a predetermined process, a clock generator for supplying a clock signal to the logic circuit, and a speed controller for controlling the operation speed of the circuit, characterized in that the clock generator changes the frequency of the clock signal by a frequency control signal while the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.
There is also provided a semiconductor integrated circuit-device comprising a logic circuit having at least first and second blocks, first and second speed controllers, and a clock generator, characterized in that clock signals of different frequencies are supplied to the first and second blocks, and the first and second speed controllers control the operating speeds of the logic circuit in the blocks in accordance with the frequencies of the clock signals supplied to the respective blocks.